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MM74HC161 * MM74HC163 Synchronous Binary Counter with Asynchronous Clear * Synchronous Binary Counter with Synchronous Clear
September 1983 Revised September 2001
MM74HC161 * MM74HC163 Synchronous Binary Counter with Asynchronous Clear * Synchronous Binary Counter with Synchronous Clear
General Description
The MM74HC161 and MM74HC163 synchronous presettable counters utilize advanced silicon-gate CMOS technology and internal look-ahead carry logic for use in high speed counting applications. They offer the high noise immunity and low power consumption inherent to CMOS with speeds similar to low power Schottky TTL. The HC161 and the HC163 are 4 bit binary counters. All flip-flops are clocked simultaneously on the LOW-to-HIGH transition (positive edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Presetting of all four flip-flops is synchronous to the rising edge of CLOCK. When LOAD is held LOW counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken HIGH before the positive edge of CLOCK the count operation will be unaffected. All of these counters may be cleared by utilizing the CLEAR input. The clear function on the MM74HC163 counter is synchronous to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clear input is held LOW. The MM74HC161 counter is cleared asynchronously. When the CLEAR is taken LOW the counter is cleared immediately regardless of the CLOCK. Two active HIGH enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be HIGH to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the HIGH level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
s Typical operating frequency: 40 MHz s Typical propagation delay; clock to Q: 18 ns s Low quiescent current: 80 A maximum (74HC Series) s Low input current: 1 A maximum s Wide power supply range: 2-6V
Ordering Code:
Order Number MM74HC161M MM74HC161SJ MM74HC161MTC MM74HC161N MM74HC163M MM74HC163SJ MM74HC163N Package Number M16A M16D MTC16 N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS005008
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MM74HC161 * MM74HC163
Connection Diagram
Truth Tables
MM74HC161 CLK CLR ENP ENT X X X X L H H H H H X H L L X H X L H L X H Load X H H H L H Function Clear Count & RC disabled Count disabled Count & RC disabled Load Increment Counter

MM74HC163 CLK CLR ENP ENT Load X H H H L H Function Clear Count & RC disabled Count disabled Count & RC disabled Load Increment Counter
X X X
L H H H H H
X H L L X H
X L H L X H

H = HIGH Level L = LOW Level X = Don't Care = LOW-to-HIGH Transition
Logic Diagram
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MM74HC161 * MM74HC163
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) (ICC) DC VCC or GND Current, per pin Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 2 0 Max 6 VCC Units V V
-0.5 to +7.0V -1.5 to VCC+1.5V -0.5 to VCC+0.5V 20 mA 25 mA 50 mA -65C to +150C
-40
+85
C
Storage Temperature Range (TSTG)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A Conditions
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 Units V V V V V V V V V V V V V V V V A A
VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = V IH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V
Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC161 * MM74HC163
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter fMAX tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL tREM tS tH tW Maximum Operating Frequency Maximum Propagation Delay, Clock to RC Maximum Propagation Delay, Clock to Q Maximum Propagation Delay, ENT to RC Maximum Propagation Delay, Clear to Q or RC Minimum Removal Time, Clear to Clock Minimum Set Up Time Clear, Load, Enable or Data to Clock Minimum Hold Time, Data from Clock Minimum Pulse Width Clock, Clear, or Load 5 16 ns ns Conditions Typ 43 30 29 18 27 10 Guaranteed Limit 30 35 34 32 38 20 30 Units MHz ns ns ns ns ns ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL Maximum Propagation Delay, Clock to RC tPLH Maximum Propagation Delay, Clock to RC tPHL Maximum Propagation Delay, Clock to Q tPLH Maximum Propagation Delay, Clock to Q tPHL Maximum Propagation Delay, ENT to RC tPLH Maximum Propagation Delay, ENT to RC tPHL Maximum Propagation Delay, Clear to RC tPHL Maximum Propagation Delay, Clear to Q tREM Minimum Removal Time Clear to Clock tS Minimum Setup Time Clear or Data to Clock tS Minimum Setup Time Load to Clock Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 10 40 45 100 32 28 88 18 15 95 30 26 85 17 14 90 28 24 80 16 14 100 32 28 100 32 28 5 27 32 215 43 37 175 35 30 205 41 35 170 34 29 195 39 33 160 32 27 220 44 37 210 42 36 125 25 21 150 30 26 135 27 23 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 4 21 25 271 54 46 220 44 37 258 52 44 214 43 36 246 49 42 202 40 34 275 55 47 260 52 45 158 32 27 190 38 32 170 34 29 4 18 21 320 64 54 260 52 44 305 61 52 253 51 43 291 58 49 238 48 41 325 66 55 315 63 54 186 37 32 225 45 38 200 41 35 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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MM74HC161 * MM74HC163
AC Electrical Characteristics
Symbol tS Parameter Minimum Setup Time Enable to Clock tH Minimum Hold Time Data from Clock tH Minimum Hold Time Enable, Load or Clear to Clock tW Minimum Pulse Width Clock, Clear, or Load tTLH, tTHL Maximum Output Rise and Fall Time tr, tf Maximum Input Rise and Fall Time CPD CIN Powert Dissipation Capacitance (Note 5) Maximum Input Capacitance
(Continued)
TA = 25C Typ 175 35 30 50 10 9 0 0 0 80 16 14 40 8 7 500 90 5 10 10 10 75 15 13 1000 500 400 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 220 44 37 63 13 11 0 0 0 100 20 17 95 19 16 1000 500 400 260 52 44 75 15 13 0 0 0 120 24 20 110 22 19 1000 500 400 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
Conditions
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
Units
(per package)
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
Logic Waveforms
Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit
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MM74HC161 * MM74HC163
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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MM74HC161 * MM74HC163
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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MM74HC161 * MM74HC163
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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MM74HC161 * MM74HC163 Synchronous Binary Counter with Asynchronous Clear * Synchronous Binary Counter with Synchronous Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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